1. Field of the Invention
The present invention relates to a memory system including an address conversion circuit, and in particular to a memory system including a memory section having a plurality of memory areas operating based on an identical principle.
2. Description of the Related Art
For accessing a memory including memory cells operating based on an identical principle, a CPU usually sends an address of the memory and a control signal designating operations such as, for example, reading and writing. The memory receives the address sent by the CPU and accesses the memory cell corresponding to the address. All the memory cells in the memory are used with a proposition of operating with an identical level of performance.
In the case of, for example, a 64-megabit dynamic random access memory (hereinafter, referred to as a xe2x80x9cDRAMxe2x80x9d), all the memory cells in the memory are accessible in an identical access time and refreshed with an identical data holding time.
The performance of the memory cells is significantly varied. The characteristics in the memory are set in accordance with the memory cell having the lowest performance in order that even the memory cell having the lowest performance is guaranteed to operate properly. Thus, even the memory cells having a higher performance cannot be effectively utilized as described specifically below.
For example, 256-megabit DRAM are known to vary in performance such as, for instance, access speed or time and data holding time.
Access time is known to be different among different memory cells in actual use. Since the resistance and length of the lines increase as the lines become thinner, the distance between a memory cell located closest and the input/output circuit and the distance between a memory cell located furthest from the input/output circuit and the input/output circuit are significantly different from each other. Accordingly, even when the memory cells per se are accessible in the same access time, the memory cell closest to the input/output circuit and the memory cell furthest from the input/output circuit turn out to have a difference of several nanoseconds in access time in actual use due to the distance therebetween.
When a memory includes a plurality of memory chips, the distance between a memory chip mounted closest to a memory control circuit and the memory control circuit and the distance between a memory chip mounted furthest from the memory control circuit and the memory control circuit is different from each other by 10 cm or more. It is known that even these two memory chips per se are accessible in the same access time, the access time in actual use to these memory chips is different by 0.5 nanoseconds or more. In this specification, the access time or speed in actual use which is influenced by the distance of the memory cell or chip from the memory control circuit will be referred to as an xe2x80x9ceffective access time or speedxe2x80x9d.
In such a case, the effective access time of the entire memory is set to the effective access time of one of all the memory cells which requires the longest time to be accessed.
Data holding time is known to be different among different memory cells by, possibly, about 50 times as demonstrated in an article in ISSCC (1995), page 245, FIG. 2. In such a case, the data holding time of the entire memory is set to the longest data holding time of all the memory cells. A longer data holding time increases the power consumption of the memory cell.
As a shorter access time is demanded in the future, the range of dispersion in the effective access time among the memory cells will be less different from the effective access time required for the memory.
This will be described regarding designing a memory operating at a frequency of 1 GHz. When the memory operates at a frequency of 1 GHz, an access time of 1 nsec. is required. As described above, the memory cell located closest to the memory control circuit and the memory cell located furthest from the memory control circuit are different in the effective access time by 0.5 nsec. or more. In order that the memory cell furthest from the memory control circuit is accessible in an effective access time of 1 nsec., the access time to the memory cell per se needs to be 0.5 nsec. or less (xe2x88x921 nsec.xe2x88x920.5 nsec.). Since it is difficult to produce memory chips accessible in an access time of 0.5 nsec. or less, the production cost of the memory is raised.
As memories are demanded to exhibit better characteristics and the performance dispersion among memory cells are unignorable with respect to the demanded level of characteristics, it will become difficult to allow all the memory cells in the memory to have the demanded level of characteristics.
As the total capacity of the memory increases, the difference in the effective access time between the memory cell furthest from the input/output circuit and/or the memory control circuit and the memory cell closest thereto further increases. Thus, it will become more difficult to allow all the memory cells in the memory to have the demanded level of characteristics.
Moreover, as the total capacity of the memory increases, all the memory cells are less likely used for the same purpose. For example, one memory area includes a part required to be accessible at a high access speed and a part required to have a long data holding time although not required to be accessible at a high access speed. Furthermore, the part required to be accessible at a high access speed includes a part required to be accessible at a high random access speed and a part required to be accessible at a high serial access speed. It will become more difficult for each of the memory cells in the memory to fulfill such various requirements corresponding thereto.
A memory system according to the present invention includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a physical address based on a correspondence between an address space and the plurality of memory regions. The correspondence is defined based on an inherent condition regarding a performance of the memory.
In one embodiment of the invention, the correspondence defines that continuous regions included in the address space are allocated to one of the plurality of memory regions in the memory.
In one embodiment of the invention, the memory includes a plurality of memory chips, and the plurality of memory regions are formed of the plurality of memory chips.
In one embodiment of the invention, the memory includes a single memory chip, and the plurality of memory regions are formed of the single memory chip.
In one embodiment of the invention, the address space and the plurality of memory regions have a plurality of correspondences therebetween. The address conversion device includes a selection device for selecting one of the plurality of correspondences between the address space and the plurality of memory regions based on selection information; and a conversion device for converting the logical address into the physical address based on the selected correspondence.
In one embodiment of the invention, the selection device includes an association memory for accumulating the plurality of correspondences; and an output device for outputting one of the plurality of correspondences accumulated in the association memory based on the selection information.
In one embodiment of the invention, the address conversion device includes a compiler for converting a logical address input from an application program into a physical address based on the correspondence.
In one embodiment of the invention, the inherent condition includes a first inherent condition regarding access speed to the memory and a second inherent condition regarding power consumption of the memory.
In one embodiment of the invention, the first inherent condition includes an inherent condition regarding a difference between a distance of a memory cell included in the memory from an input/output circuit and a distance of another memory cell included in the memory from the input/output circuit, an inherent condition regarding the level of an operating frequency of a bus, and an inherent condition regarding the level of an operating voltage of the bus, and the second inherent condition includes an inherent condition regarding the level of a threshold voltage of a transistor included in the memory and an inherent condition regarding a date holding time at standby.
In one embodiment of the invention, the first inherent condition includes an inherent condition regarding a difference between a distance of a memory cell included in the memory from the address conversion device and a distance of another memory cell included in the memory from the address conversion device, an inherent condition regarding the level of an operating frequency of a bus, and an inherent condition regarding the level of an operating voltage of the bus; and the second inherent condition includes an inherent condition regarding the level of a threshold voltage of a transistor included in the memory and an inherent condition regarding a data holding time at standby.
According to the present invention, the address conversion device of a memory system converts a logical address into a physical address based on the correspondence between the address space and the plurality of memory regions in the memory. The correspondence is defined by the inherent conditions regarding the performance of the memory. Therefore, the memory system according to the present invention is allowed to perform to its full capability without being influenced by memory cells or chips having poor capability.
Thus, the invention described herein makes possible the advantages of (1) providing a memory system operable at a high level of characteristics without being influenced by a memory cell having the lowest level of performance; (2) providing a memory system operable with a sufficiently short effective access time without being influenced by a memory cell requiring the longest effective access time; and (3) providing a memory system operable with reduced power consumption without being influenced by a memory cell having the largest power consumption.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.